`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:38:45 12/16/2024
// Design Name:   Main
// Module Name:   C:/CYH/ISE/13/Lab13/test01.v
// Project Name:  Lab13
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test01;

	// Inputs
	reg clk;
	reg [1:0] SW;

	// Outputs
	wire [2:0] which;
	wire [7:0] seg;

	// Instantiate the Unit Under Test (UUT)
	Main uut (
		.clk(clk), 
		.SW(SW), 
		.which(which), 
		.seg(seg)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		SW = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		SW=2'B10;

	end
    always #0.001 clk = ~clk;  
endmodule

